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UT54ACS244/UT54ACTS244
Radiation-Hardened Octal Buffers & Line Drivers, Three-State Outputs
FEATURES Three-state outputs drive bus lines or buffer memory address registers radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack DESCRIPTION The UT54ACS244 and the UT54ACTS244 are non-inverting octal buffer and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE
INPUTS 1G, 2G L L H A L H X OUTPUT Y L H Z
PINOUTS 20-Pin DIP Top View
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
20-Lead Flatpack Top View
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
LOGIC SYMBOL
1G 1A1 (1) (2) EN (18) (16) (14) (12) 1Y1 1Y2 1Y3 1Y4
(4) 1A2 (6) 1A3 (8) 1A4 (19) (11)
2G 2A1
EN (9) (7) (5) (3) 2Y1 2Y2 2Y3
2Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
(13) 2A2 (15) 2A3 (17) 2A4
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UT54ACS244/UT54ACTS244
LOGIC DIAGRAM
1G (1) 2G (19)
1A1
(2)
(18)
1Y1
2A1
(11)
(9)
2Y1
1A2
(4)
(16)
1Y2
2A2
(13)
(7)
2Y2
1A3
(6)
(14)
1Y3
2A3
(15)
(5)
2Y3
1A4
(8)
(12)
1Y4
2A4
(17)
(3)
2Y4
RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence LIMIT 1.0E6 80 120 1.0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2
Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table 2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS SYMBOL VDD VI/O TSTG TJ TLS
JC
PARAMETER Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current Maximum power dissipation
LIMIT -0.3 to 7.0 -.3 to VDD +.3 -65 to +150 +175 +300 20 10 1
UNITS V V C C C C/W mA W
II PD
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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UT54ACS244/UT54ACTS244
RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC PARAMETER Supply voltage Input voltage any pin Temperature range LIMIT 4.5 to 5.5 0 to VDD -55 to + 125 UNITS V V C
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DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL PARAMETER Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage 3 ACTS ACS High-level output voltage 3 ACTS ACS Output current10 (Sink) IOH Output current10 (Source) IOZ IOS Ptotal IDDQ IDDQ Three-state output leakage current Short-circuit output current 2 ,4 ACTS/ACS Power dissipation 2,8,9 Quiescent Supply Current Quiescent Supply Current Delta ACTS VIN = VDD or VSS IOL = 12.0mA IOL = 100 A IOH = -12.0mA IOH = -100 A VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = VDD - 0.4V VO = VDD and VSS VO = VDD and VSS CL = 50pF VDD = 5.5V For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 Output capacitance 5 = 1MHz @ 0V = 1MHz @ 0V 15 15 pF pF -30 -300 30 300 2.0 10 1.6 A mA mW/ MHz A mA -12 mA .7VDD VDD - 0.25 12 .5VDD .7VDD -1 1 0.40 0.25 CONDITION MIN MAX 0.8 .3VDD UNIT V
VIH
V
IIN VOL
A V
VOH
V
IOL
mA
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UT54ACS244/UT54ACTS244
Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested.
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AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ Input to Yn Input to Yn G low to Yn active G low to Yn active G high to Yn three-state G high to Yn three-state PARAMETER MINIMUM 1 1 2 2 2 2 MAXIMUM 11 11 12 12 12 12 UNIT ns ns ns ns ns ns
Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si).
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